1. Field of Invention
The present invention relates a Liquid Crystal Display ("LCD") and a method for fabricating an LCD which prevents a line open condition of conductive lines located at a step difference portion.
2. Discussion of Related Art
FIGS. 1 and 2 illustrate an LCD according to related art, in which FIG. 1 is a plan view and FIG. 2 is a cross-sectional view along a line I--I in FIG. 1.
An active layer 11 having a source region 11S, a channel region 11C and a drain region 11D is formed on a substrate 100. A gate line 13L includes a gate electrode 13G and overlaps the channel region 11C. A gate insulating layer is formed underneath the gate electrode 13G and the gate line 13L, and is thereby isolated with the active layer 11.
An insulating interlayer 14 is formed to cover the exposed surface of the substrate including the gate electrode 13G and the gate line 13L. Contact holes to expose portions of the source region 11S and the drain region 11D are formed in the insulating interlayer 14, respectively. A data line 15L having a source electrode 15S connected to the source region 11S is formed on the insulating interlayer 14.
A drain electrode 15D is connected to the exposed drain electrode 11D. Herein, the gate line 13L and the data line 15L cross over each other and define a matrix to form a plurality of pixel elements. A passivation layer 16 is arranged to cover the exposed surface of the substrate including the data line 15L. A contact hole to expose a portion of the drain electrode 15D is formed in the passivation layer 16. A pixel electrode 17 is formed on the passivation layer 16 and is connected to the exposed drain electrode 15D.
FIGS. 3A to 3D show cross-sectional views of a method of fabricating an LCD according to a related art shown in FIGS. 1 and 2.
Referring to FIG. 3A, an amorphous silicon layer is deposited on a substrate 100 and is crystallized. The crystallized silicon layer is etched via photolithography to form an active layer 11.
An insulating layer for forming a gate insulating layer and a conductive layer for forming a gate line are deposited sequentially on the exposed surface of the substrate including the active layer 11. The conductive layer is etched via photolithography to form a gate electrode 13G and a gate line 13L and then, the insulating layer is etched using the gate electrode 13G as a mask to form a gate insulating layer 12.
A source region 11S and a drain region 11D are formed in the active layer by doping impurities in the exposed portion of the active layer 11 using the gate line 13L and the gate electrode 13G as a doping mask. The channel region 11C is defined between the source region 11S and the drain regions 11D.
Referring to FIG. 3B, an insulating interlayer 14 is deposited on the exposed surface of the substrate including the gate line 13L and the gate electrode 13G. Then, contact holes H1 and H2 exposing the portions of the source region 11S and the drain region 11D are formed in the insulating interlayer 14, respectively, by etching the insulating interlayer 14 via photolithography.
A conductive layer for forming a data line including a source electrode and a drain electrode, for example, an Al layer, an Al alloy layer or the like, is deposited on the exposed surface of the substrate and etched via photolithography to form a source electrode 15S, a data line 15L and a drain electrode 15D. The source electrode 15S is connected to the source region 11S, the data line 15L is extended from the source electrode 15S and the drain electrode 15D is connected to the drain region 11D.
Referring to FIG. 3C, a passivation layer 16 is deposited on the exposed surface of the substrate and etched via photolithography to form a contact hole exposing a portion of the drain electrode 15D.
Referring to FIG. 3D, a transparent conductive layer 16, for example, Indium Tin Oxide ("ITO") layer is deposited on the exposed surface of the substrate and etched via photolithography to form a pixel electrode 17 connected to the drain electrode 15D.
However, there are disadvantages in that line open conditions occur in the gate line or the date line, especially at locations at or near the crossing portion of the gate line 15L and the data line 11L and the contact hole portions in the related art LCD. The line open condition is described as follows referring to FIG. 4.
FIG. 4 is a cross-sectional drawing showing the line open condition occurring during the manufacturing process of the LCD according to the related art.
The gate line 13L including the gate electrode 13G is formed on the substrate 100 and the insulating interlayer 14 is formed thereon. At a location where the step coverage of the insulating interlayer 14, which covers the portion of the step difference of the gate line 13L, is bad, the degree of the side slope increases more and more.
Since the conductive layer for forming the data line including the source electrode is deposited on the insulating interlayer 14 via a sputtering method, the step coverage of the conductive layer is very poor and the degree of the side slope increases more and more. Additionally, the passivation layer 16 is deposited on the data line 15L including the source electrode 15S and the drain electrode 15D having sloped sides. However, since the step coverage of the passivation layer 16 is bad, the passivation layer 16 is very thinly deposited on the slope portion.
Accordingly, stress is concentrated on the slope portion and then, cracks are generated in the conductive layer or insulating layer. Since the passivation layer 16 is deposited in the low temperature atmosphere, the rate of the occurrence of pin holes which cause line open conditions is higher in the slope portion than in any other portion.
Successively, the ITO layer for forming the pixel electrode is deposited on the passivation layer 16 and the ITO layer is etched by ITO etchant, which is a mixture solution of FeCl.sub.2, HCl and HNO.sub.3. The ITO etchant penetrates into the passivation layer 16 through the pin holes and cracks form and the ITO etchant melts the data line which includes the source electrode and the drain electrode, thereby causing an open line condition in the data line or the drain electrode.